sai685
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Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 // testbench here // or browse Examples // fill 20 pos (write) // fork // read // 10 pop -- 12 // write // 12 push -- 10 // join // compare - fifo size - (32)full/(0)empty signal // bit[31:0] queue[$]; // // queue.push_back(item) // queue.pop_front(item) // queue = {}; queue.size() == 0 /32 module fifo_top_tb; reg wr_clk,rd_clk; reg[31:0] data_in; wire[31:0] data_out; wire rd_empty,wr_full; reg reset_w; reg reset_r; reg write_enable,read_enable; fifo_top top1(.wdata(data_in), .rdata(data_out), .wclk(wr_clk), .rclk(rd_clk), .wreset_b(reset_w), .rreset_b(reset_r), .write(write_enable) , .read(read_enable), .rempty(rd_empty), .wfull(wr_full)); bit[31:0] queue[$]; int i,j; reg count; reg queue_size; task initilize; begin write_enable =0; read_enable =0; wr_clk=0; rd_clk=0; data_in=0; $monitor ("wr_clk=%d,reset_w=%d,reset_r=%d,write_enable=%d,read_enable=%d,data_in=%d,data_out=%d,wr_full=%d,rd_empty=%d" ,wr_clk,reset_w,reset_r,write_enable,read_enable,data_in,data_out,wr_full,rd_empty); end endtask task wrreset; begin reset_w=0; // asserted data_in=0; write_enable =0; read_enable =0; end #10 reset_w =~reset_w; endtask task write(input w,r, input [4:0]no_of_times); reg [4:0] h; begin for(h = 0;h<=no_of_times;h=h+1) begin #10 @(posedge wr_clk) data_in = $random; write_enable=w; read_enable=r; end end endtask task writeread(input w,r, input [4:0] no_of_times); begin write(w,r,no_of_times); read(w,r,no_of_times); end endtask initial wr_clk=0; always #20wr_clk= ~wr_clk; initial begin wrreset; initilize; write(1,0,20); $display($time,"write operation is over \n"); //#10read(0,1,15); #100 $finish ; end task rdreset; begin reset_r=0; //asserted #10 reset_r=~reset_r; end endtask task read(input w,r, input [4:0]no_of_times); reg[4:0] h; begin $display($time,"COntrol has entered the loop "); for(h = 0;h<=no_of_times;h=h+1) begin @(posedge rd_clk) begin write_enable=w; read_enable=r; end end end #10 reset_r=~reset_r; endtask initial begin rdreset; initilize; /*write(1,0,15);*/ read(0,1,20); $display($time,"read operation is over \n"); #100 $finish ; end initial rd_clk=0; always #20 rd_clk= ~rd_clk; initial begin $dumpfile("fifo_top_tb.vcd"); $dumpvars(wr_clk,reset_w,reset_r,write_enable,read_enable,data_in,data_out,wr_full,rd_empty); end initial #2$monitor("wr_clk=%d,reset_w=%d,reset_r=%d,write_enable=%d,read_enable=%d,data_in=%d,data_out=%d,wr_full=%d,rd_empty=%d" ,wr_clk,reset_w,reset_r,write_enable,read_enable,data_in,data_out,wr_full,rd_empty); initial #800$finish; initial fork for(i=0;i<=12;i=i+1) begin queue.push_back(data_in[i]); $display("queue[i]=%p",queue[i]); end for(j=0;j<=10;j=j+1) begin queue.pop_front(); $display("queue[j]=%p",queue[j]); end join always @(posedge wr_clk ) begin if (reset_w ) begin count = 0; end else if(count!=32 && write_enable) begin count=count +1; end else begin count=count; end end //READ always @(posedge rd_clk) begin if(reset_r) begin count=32; end else if (count!=0 && read_enable) begin count=count-1; end // Concurrent read and write.. no change in count else begin count = count; end end // *** Update the flags // // First, update the empty flag. // always @(count) begin if(queue_size==32) begin $display("full"); end end // Update the full flag // always @(count) begin if(queue_size==0) begin $display("empty"); end else begin $display("neither full nor empty"); end end initial begin $dumpfile("fifo_top_tb.vcd"); $dumpvars(1,data_in,data_out,wr_clk,rd_clk,wr_full,rd_empty); end endmodule //Design here module fifo_top #( parameter DEPTH = 32, WIDTH = 32, ADDR = 5 ) ( input wire write, wreset_b, wclk, read, rreset_b, rclk, input wire [WIDTH-1:0] wdata, output wire [WIDTH-1:0] rdata, output wire rempty, wfull ); // function to convert from gray to binary function [ADDR:0] G2B_Fn; input [ADDR:0] gray; reg [ADDR:0] binary; integer i; begin binary[ADDR] = gray [ADDR]; for (i=ADDR-1;i >= 0;i=i-1) binary[i] = (binary[i+1] ^ gray[i]); G2B_Fn = binary; end endfunction // declare connecting wires wire [ADDR:0] wptr_b,wptr_g, // binary and gray signals from write pointer rptr_b,rptr_g; // binary and gray signals from read pointer reg [ADDR:0] g2b_wd_op, // function G2B_Fn output in the write domain g2b_rd_op; // function G2B_Fn output in the read domain wire [ADDR:0] g2b_wd_ip, // function G2B_Fn input in the write domain g2b_rd_ip; // function G2B_Fn input in the read domain //assign intermediate wires always @(g2b_wd_ip or g2b_rd_ip) begin g2b_wd_op = G2B_Fn(g2b_wd_ip); g2b_rd_op = G2B_Fn(g2b_rd_ip); end // instantiate write pointer pointer wptr( .clk(wclk), .reset_b(wreset_b), .op(write), .fifo_status(wfull), .gray(wptr_g), .binary(wptr_b) ); //instantiate read pointer pointer rptr( .clk(rclk), .reset_b(rreset_b), .op(read), .fifo_status(rempty), .gray(rptr_g), .binary(rptr_b) ); //instantiate memory module memory m1( .clk(wclk), .reset_b(wreset_b), .write(write), .wfull(wfull), .waddr(wptr_b[ADDR-1:0]), .raddr(rptr_b[ADDR-1:0]), .wdata(wdata), .rdata(rdata) ); //instantiate read->write synchronizer sync_r2w syncr2w( .clk(wclk), .reset_b(wreset_b), .rptr(rptr_g), .rptr_wr(g2b_wd_ip) ); //instantiate write->read synchronizer sync_w2r syncw2r( .clk(rclk), .reset_b(rreset_b), .wptr(wptr_g), .wptr_rd(g2b_rd_ip) ); //instantiate write domain comparator compare_wr cmp_wr( .rptr(g2b_wd_op), .wptr(wptr_b), .full(wfull) ); //instantiate write domain comparator compare_rd cmp_rd( .rptr(rptr_b), .wptr(g2b_rd_op), .empty(rempty) ); endmodule module pointer #( parameter ADDR = 5 // parameterized size of pointers ) ( input wire clk,reset_b,op,fifo_status, // input-output declaration output reg [ADDR:0] gray,binary ); integer i; always@(posedge clk, negedge reset_b) begin if(~reset_b) begin binary = 'd0; gray = 'd0; end else if(op & ~fifo_status) binary <= binary + 1; end always @(binary) begin gray[ADDR] = binary[ADDR]; for (i=ADDR-1;i>=0;i=i-1) gray[i] = binary[i] ^ binary[i+1]; end endmodule module memory #( parameter DEPTH = 32, // parameter declaration WIDTH = 32, ADDR = 5 ) ( input wire clk, reset_b, write, wfull, // input - output declaration input wire [ADDR-1:0] waddr, raddr, input wire [WIDTH-1:0] wdata, output wire [WIDTH-1:0] rdata ); integer i; // creating memory reg [WIDTH-1:0] sram [DEPTH-1:0]; // writing in the memory always @(posedge clk, negedge reset_b) begin if(~reset_b) begin for(i=0;i<DEPTH;i = i+1) sram[i] <= 'h0; end else if(write & ~wfull) sram[waddr] <= wdata; end // reading a memory location assign rdata = sram[raddr]; endmodule // to synchronize from fast clock domain to slow clock domain (write -> read) module sync_w2r #( parameter ADDR = 5 ) ( input wire clk, reset_b, input wire [ADDR:0] wptr, output reg [ADDR:0] wptr_rd ); reg [ADDR:0] q; always @(posedge clk or negedge reset_b) begin if(~reset_b) begin q <= 'd0; wptr_rd <= 'd0; end else begin q <= wptr; wptr_rd <= q; end end endmodule // to synchronize from slow clock domain to fast clock domain (read -> write) module sync_r2w #( parameter ADDR = 5 ) ( input wire clk, reset_b, input wire [ADDR:0] rptr, output reg [ADDR:0] rptr_wr ); reg [ADDR:0] q; always @(posedge clk or negedge reset_b) begin if(~reset_b) begin q <= 'd0; rptr_wr <= 'd0; end else begin q <= rptr; rptr_wr <= q; end end endmodule module compare_wr #( parameter ADDR = 5 // declare parameter for memory address ) ( input wire [ADDR:0] rptr,wptr, // declare inputs and outputs output wire full ); //check for full condition: Write pointer has wrapped around but read pointer has not assign full = (wptr[ADDR] != rptr[ADDR]) & (wptr[ADDR-1:0] == rptr[ADDR-1:0]); endmodule module compare_rd #( parameter ADDR = 5 // declare parameter for memory address ) ( input wire [ADDR:0] rptr,wptr, // declare inputs and outputs output wire empty ); //check for full condition: WRITE and READ pointers have NOT wrapped around assign empty = wptr[ADDR:0] == rptr[ADDR:0]; endmodule