Technology Nodes & Operation Frequency

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ivlsi

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Hi All,

How are technology nodes related with operation frequency?

Let's say, for a design working on 500MHz, what tech node should be chosen - 25nm? 45nm? other?

Thank you!
 

Well, the frequency is also related to the voltage your run your design, and how many logic you have between two clock elements, not purely dependent of the technology node.
 
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    ivlsi

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ok, let's say it's a mid-size chip ... as for the voltage, nowadays std cells work on 3.3V or am I wrong?
As for the amount of logic between two clock elements, let's say it's not an issue (from my point of view) because it always might be pipe-lined or re-balanced.
So, how should I choose what tech node should I choose?
For example, I was recently told that running a design (Cache Controller) @500MHz on 45nm process might be a BIG challenge...
What's your opinion?
 

For the voltage std cell, I made since year 2000, more than 15 designs at 0v72, 0v90, 1v20, 1v80 and only one 3v30.
The max frequency, is the time the data need to go from the q pin of the flop to the d pin of the flop, through the logic, then the amount of logic between the flop is important, then you rtl code need to take care of that.

Also to clarify what is a mid size design, 100kgate, and how said before how many pipeline you have to reach the frequency you need.

It is always a trade off between timing area and power for certain design.

For sure if you flop has a setup of 20ns it will be impossible .
 
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    ivlsi

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Re: Technology Nodes & Operation Frequency

hm... as for the ff setup time, does not it depends on tech node? Is there a correlation between them?

As the CMOS is shorter (lower tech node) as its Tsu should be smaller... Am I wrong?

What does the setup time of FF depend on? Internal capacitance, etc?

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what's setup time usually have the 45nm and 25nm flops?

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btw, what prons and cons in increasing the synthesis clock frequency instead of defining the clock uncertainty? As for hold uncertainty, is this for OCV?
 

Operating frequency is not directly related to technology node. Moving down technology nodes it is possible to get lower delays and hence push frequency higher. But the frequency is highly dependent on supply voltage as well as how you design your circuit (delay between to flops), pipeline depth, clock design as well as the allowed power dissipation and process variation. As for supply voltage, 32/28/20nm nodes have supply voltages in the range of 1.2 to 0.9V. Everything below 20nm i.e. FinFETs will possibly run at lower voltages. SoCs run at 1.2 to 1.4GHz at 32nm node and will possibly run faster at lower technology nodes. Technology scaling allows higher frequency due to lower intrinsic delay, however it is definitely not the deciding factor.
 

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