BrownieHaHa
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Hello everyone, I have a question regarding process node normalization that may seem a bit peculiar (I don't know which Forum suits my topic so I post it here).
Firstly, let me explain the origin of this question. In recent chip designs, particularly in AI chip design such as NPUs, there's been an increasing emphasis on energy efficiency. This metric characterizes the comprehensive performance of a chip in terms of energy utilization, computing speed, and overall performance. Of course, there's a lot of discussion and even controversy online about this metric, but let's set that aside for now.
Clearly, efficiency is influenced by many factors, among which process node is one. From articles of different companies, universities, and research institutions, it's evident that there's a wide variety of process nodes being used, ranging from 40 nm to the most advanced 3 nm nodes.
However, to showcase the advantages of one's own design, it's necessary to compare energy efficiency metric through a process called "normalization," which is used quite broadly and somewhat imprecisely in numerous articles and journals.
I've been preparing related content recently, but upon deeper analysis and statistics, I've found it's not as straightforward as I imagined. Firstly, there isn't a complete data source; IRDS provides a roadmap from 2016 to the present, but data on the changes in energy efficiency (scaling) seems to be available only from 2022 onwards (unless I missed something). ITRS (the predecessor of IRDS) also doesn't seem to have statistical data on this metric (since it's a relatively new concept). Therefore, from a data source perspective, I'm stuck.
Another issue is that we know chip process nodes have undergone significant evolution from planar to finFET technologies. Planar processes could potentially be normalized using simple methods (but still confusing for me), but in advanced nodes, especially those named through equivalent methods, normalization to the same process node becomes even more challenging.
In conclusion, I would like to solicit opinions and help from everyone on this matter. Thank you very much.
Firstly, let me explain the origin of this question. In recent chip designs, particularly in AI chip design such as NPUs, there's been an increasing emphasis on energy efficiency. This metric characterizes the comprehensive performance of a chip in terms of energy utilization, computing speed, and overall performance. Of course, there's a lot of discussion and even controversy online about this metric, but let's set that aside for now.
Clearly, efficiency is influenced by many factors, among which process node is one. From articles of different companies, universities, and research institutions, it's evident that there's a wide variety of process nodes being used, ranging from 40 nm to the most advanced 3 nm nodes.
However, to showcase the advantages of one's own design, it's necessary to compare energy efficiency metric through a process called "normalization," which is used quite broadly and somewhat imprecisely in numerous articles and journals.
I've been preparing related content recently, but upon deeper analysis and statistics, I've found it's not as straightforward as I imagined. Firstly, there isn't a complete data source; IRDS provides a roadmap from 2016 to the present, but data on the changes in energy efficiency (scaling) seems to be available only from 2022 onwards (unless I missed something). ITRS (the predecessor of IRDS) also doesn't seem to have statistical data on this metric (since it's a relatively new concept). Therefore, from a data source perspective, I'm stuck.
Another issue is that we know chip process nodes have undergone significant evolution from planar to finFET technologies. Planar processes could potentially be normalized using simple methods (but still confusing for me), but in advanced nodes, especially those named through equivalent methods, normalization to the same process node becomes even more challenging.
In conclusion, I would like to solicit opinions and help from everyone on this matter. Thank you very much.