TB simulation error's

Hello, i am trying to learn how to implement an SPI Slave for work. this is the my first time writing any module so i decided to try to build a test bench around someones slave module i found online. i wrote the test bench but when i go to simulation i get a bunch of signals showing U and im not sure why i also receive a warning coming from the test bench. im not really sure what the problem is any help is appreciated Ive attached all relevant information below.

SPI SLAVE

1. --------------------------------------------------------------------------------
2. -- PROJECT: SPI SLAVE FOR FPGA
3. --------------------------------------------------------------------------------
4. -- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
5. -- LICENSE: The MIT License, please read LICENSE file
6. -- WEBSITE: https://github.com/jakubcabal/spi-fpga
7. --------------------------------------------------------------------------------
8. 
   
9. library IEEE;
10. use IEEE.STD_LOGIC_1164.ALL;
11. use IEEE.NUMERIC_STD.ALL;
12. use IEEE.MATH_REAL.ALL;
13. 
    
14. -- THE SPI SLAVE MODULE SUPPORT ONLY SPI MODE 0 (CPOL=0, CPHA=0)!!!
15. 
    
16. entity SPI_SLAVE1 is
17. Generic (
18. WORD_SIZE : natural := 8 -- size of transfer word in bits, must be power of two
19. );
20. Port (
21. CLK : in std_logic; -- system clock
22. RST : in std_logic; -- high active synchronous reset
23. -- SPI SLAVE INTERFACE
24. SCLK : in std_logic; -- SPI clock
25. CS_N : in std_logic; -- SPI chip select, active in low
26. MOSI : in std_logic; -- SPI serial data from master to slave
27. MISO : out std_logic; -- SPI serial data from slave to master
28. -- USER INTERFACE
29. DIN : in std_logic_vector(WORD_SIZE-1 downto 0); -- data for transmission to SPI master
30. DIN_VLD : in std_logic; -- when DIN_VLD = 1, data for transmission are valid
31. DIN_RDY : out std_logic; -- when DIN_RDY = 1, SPI slave is ready to accept valid data for transmission
32. DOUT : out std_logic_vector(WORD_SIZE-1 downto 0); -- received data from SPI master
33. DOUT_VLD : out std_logic -- when DOUT_VLD = 1, received data are valid
34. );
35. end entity;
36. 
    
37. architecture RTL of SPI_SLAVE1 is
38. 
    
39. constant BIT_CNT_WIDTH : natural := natural(ceil(log2(real(WORD_SIZE))));
40. 
    
41. signal sclk_meta : std_logic;
42. signal cs_n_meta : std_logic;
43. signal mosi_meta : std_logic;
44. signal sclk_reg : std_logic;
45. signal cs_n_reg : std_logic;
46. signal mosi_reg : std_logic;
47. signal spi_clk_reg : std_logic;
48. signal spi_clk_redge_en : std_logic;
49. signal spi_clk_fedge_en : std_logic;
50. signal bit_cnt : unsigned(BIT_CNT_WIDTH-1 downto 0);
51. signal bit_cnt_max : std_logic;
52. signal last_bit_en : std_logic;
53. signal load_data_en : std_logic;
54. signal data_shreg : std_logic_vector(WORD_SIZE-1 downto 0);
55. signal slave_ready : std_logic;
56. signal shreg_busy : std_logic;
57. signal rx_data_vld : std_logic;
58. 
    
59. begin
60. 
    
61. -- -------------------------------------------------------------------------
62. -- INPUT SYNCHRONIZATION REGISTERS
63. -- -------------------------------------------------------------------------
64. 
    
65. -- Synchronization registers to eliminate possible metastability.
66. sync_ffs_p : process (CLK)
67. begin
68. if (rising_edge(CLK)) then
69. sclk_meta <= SCLK;
70. cs_n_meta <= CS_N;
71. mosi_meta <= MOSI;
72. sclk_reg <= sclk_meta;
73. cs_n_reg <= cs_n_meta;
74. mosi_reg <= mosi_meta;
75. end if;
76. end process;
77. 
    
78. -- -------------------------------------------------------------------------
79. -- SPI CLOCK REGISTER
80. -- -------------------------------------------------------------------------
81. 
    
82. -- The SPI clock register is necessary for clock edge detection.
83. spi_clk_reg_p : process (CLK)
84. begin
85. if (rising_edge(CLK)) then
86. if (RST = '1') then
87. spi_clk_reg <= '0';
88. else
89. spi_clk_reg <= sclk_reg;
90. end if;
91. end if;
92. end process;
93. 
    
94. -- -------------------------------------------------------------------------
95. -- SPI CLOCK EDGES FLAGS
96. -- -------------------------------------------------------------------------
97. 
    
98. -- Falling edge is detect when sclk_reg=0 and spi_clk_reg=1.
99. spi_clk_fedge_en <= not sclk_reg and spi_clk_reg;
100. -- Rising edge is detect when sclk_reg=1 and spi_clk_reg=0.
101. spi_clk_redge_en <= sclk_reg and not spi_clk_reg;
102. 
     
103. -- -------------------------------------------------------------------------
104. -- RECEIVED BITS COUNTER
105. -- -------------------------------------------------------------------------
106. 
     
107. -- The counter counts received bits from the master. Counter is enabled when
108. -- falling edge of SPI clock is detected and not asserted cs_n_reg.
109. bit_cnt_p : process (CLK)
110. begin
111. if (rising_edge(CLK)) then
112. if (RST = '1') then
113. bit_cnt <= (others => '0');
114. elsif (spi_clk_fedge_en = '1' and cs_n_reg = '0') then
115. if (bit_cnt_max = '1') then
116. bit_cnt <= (others => '0');
117. else
118. bit_cnt <= bit_cnt + 1;
119. end if;
120. end if;
121. end if;
122. end process;
123. 
     
124. -- The flag of maximal value of the bit counter.
125. bit_cnt_max <= '1' when (bit_cnt = WORD_SIZE-1) else '0';
126. 
     
127. -- -------------------------------------------------------------------------
128. -- LAST BIT FLAG REGISTER
129. -- -------------------------------------------------------------------------
130. 
     
131. -- The flag of last bit of received byte is only registered the flag of
132. -- maximal value of the bit counter.
133. last_bit_en_p : process (CLK)
134. begin
135. if (rising_edge(CLK)) then
136. if (RST = '1') then
137. last_bit_en <= '0';
138. else
139. last_bit_en <= bit_cnt_max;
140. end if;
141. end if;
142. end process;
143. 
     
144. -- -------------------------------------------------------------------------
145. -- RECEIVED DATA VALID FLAG
146. -- -------------------------------------------------------------------------
147. 
     
148. -- Received data from master are valid when falling edge of SPI clock is
149. -- detected and the last bit of received byte is detected.
150. rx_data_vld <= spi_clk_fedge_en and last_bit_en;
151. 
     
152. -- -------------------------------------------------------------------------
153. -- SHIFT REGISTER BUSY FLAG REGISTER
154. -- -------------------------------------------------------------------------
155. 
     
156. -- Data shift register is busy until it sends all input data to SPI master.
157. shreg_busy_p : process (CLK)
158. begin
159. if (rising_edge(CLK)) then
160. if (RST = '1') then
161. shreg_busy <= '0';
162. else
163. if (DIN_VLD = '1' and (cs_n_reg = '1' or rx_data_vld = '1')) then
164. shreg_busy <= '1';
165. elsif (rx_data_vld = '1') then
166. shreg_busy <= '0';
167. else
168. shreg_busy <= shreg_busy;
169. end if;
170. end if;
171. end if;
172. end process;
173. 
     
174. -- The SPI slave is ready for accept new input data when cs_n_reg is assert and
175. -- shift register not busy or when received data are valid.
176. slave_ready <= (cs_n_reg and not shreg_busy) or rx_data_vld;
178. -- The new input data is loaded into the shift register when the SPI slave
179. -- is ready and input data are valid.
180. load_data_en <= slave_ready and DIN_VLD;
181. 
     
182. -- -------------------------------------------------------------------------
183. -- DATA SHIFT REGISTER
184. -- -------------------------------------------------------------------------
185. 
     
186. -- The shift register holds data for sending to master, capture and store
187. -- incoming data from master.
188. data_shreg_p : process (CLK)
189. begin
190. if (rising_edge(CLK)) then
191. if (load_data_en = '1') then
192. data_shreg <= DIN;
193. elsif (spi_clk_redge_en = '1' and cs_n_reg = '0') then
194. data_shreg <= data_shreg(WORD_SIZE-2 downto 0) & mosi_reg;
195. end if;
196. end if;
197. end process;
198. 
     
199. -- -------------------------------------------------------------------------
200. -- MISO REGISTER
201. -- -------------------------------------------------------------------------
202. 
     
203. -- The output MISO register ensures that the bits are transmit to the master
204. -- when is not assert cs_n_reg and falling edge of SPI clock is detected.
205. miso_p : process (CLK)
206. begin
207. if (rising_edge(CLK)) then
208. if (load_data_en = '1') then
209. MISO <= DIN(WORD_SIZE-1);
210. elsif (spi_clk_fedge_en = '1' and cs_n_reg = '0') then
211. MISO <= data_shreg(WORD_SIZE-1);
212. end if;
213. end if;
214. end process;
215. 
     
216. -- -------------------------------------------------------------------------
217. -- ASSIGNING OUTPUT SIGNALS
218. -- -------------------------------------------------------------------------
220. DIN_RDY <= slave_ready;
221. DOUT <= data_shreg;
222. DOUT_VLD <= rx_data_vld;
223. 
     
224. end architecture;

TB for SPI SLAVE

1. library IEEE;
2. use IEEE.std_logic_1164.all;
3. use IEEE.numeric_std.all;
4. use IEEE.MATH_REAL.ALL;
5. 
   
6. entity Spi_practice2_tb is
7. end Spi_practice2_tb;
8. 
   
9. architecture bench of Spi_practice2_tb is
10. 
    
11. constant WORD_SIZE : integer := 8;
12. constant clock_period: time := 10 ns;
13. constant BIT_CNT_WIDTH : natural:= natural(ceil(log2(real(WORD_SIZE))));
14. 
    
15. component SPI_SLAVE1
17. port(
18. CLK,RST,SCLK,CS_N,MOSI,DIN_VLD: in std_logic;
19. MISO,DIN_RDY,DOUT_VLD: out std_logic;
20. DIN: in std_logic_vector(WORD_SIZE-1 downto 0);
21. DOUT: out std_logic_vector(WORD_SIZE-1 downto 0)
22. );
23. end component;
24. 
    
25. signal CLK,RST,SCLK,CS_N,MOSI,DIN_VLD: std_logic;
26. signal MISO,DIN_RDY,DOUT_VLD: std_logic;
27. signal DIN: std_logic_vector(WORD_SIZE-1 downto 0);
28. signal DOUT: std_logic_vector(WORD_SIZE-1 downto 0);
29. signal stop_the_clock:boolean;
30. 
    
31. 
    
32. signal sclk_meta : std_logic;
33. signal cs_n_meta : std_logic;
34. signal mosi_meta : std_logic;
35. signal sclk_reg : std_logic;
36. signal cs_n_reg : std_logic;
37. signal mosi_reg : std_logic;
38. signal spi_clk_reg : std_logic;
39. signal spi_clk_redge_en : std_logic;
40. signal spi_clk_fedge_en : std_logic;
41. signal bit_cnt : unsigned(BIT_CNT_WIDTH-1 downto 0);
42. signal bit_cnt_max : std_logic;
43. signal last_bit_en : std_logic;
44. signal load_data_en : std_logic;
45. signal data_shreg : std_logic_vector(WORD_SIZE-1 downto 0);
46. signal slave_ready : std_logic;
47. signal shreg_busy : std_logic;
48. signal rx_data_vld : std_logic;
49. 
    
50. 
    
51. begin
52. PM: entity work.SPI_SLAVE1
53. port map (CLK => CLK,
54. RST => RST,
55. SCLK => SCLK,
56. CS_N => CS_N,
57. MOSI => MOSI,
58. DIN => DIN,
59. DIN_VLD => DIN_VLD,
60. MISO => MISO,
61. DIN_RDY => DIN_RDY,
62. DOUT => DOUT,
63. DOUT_VLD => DOUT_VLD);
64. 
    
65. process
66. begin
67. RST <= '1';
68. RST <= '0';
69. wait for clock_period;
70. spi_clk_fedge_en <= '1';
71. cs_n_reg <= '0';
72. wait for clock_period;
73. DIN_VLD <= '1';
74. cs_n_reg <= '1';
75. rx_data_vld <= '1';
76. wait;
77. end process;
78. 
    
79. process -- clock generation
80. begin
81. while not stop_the_clock loop
82. CLK <= '0';
83. wait for clock_period / 2;
84. CLK <= '1';
85. wait for clock_period / 2;
86. end loop;
87. wait;
88. 
    
89. 
    
90. end process;
91. end;