rocking_vlsi
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- Jun 9, 2011
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Hi
Please read the code below and
//////////////////////////////////////////////////////////
reg gbl_reg ;
reg temp1;
task simple_task
input a;
begin
gbl_reg=a;
end
endtask
always@(*)
temp1=0;
simple_task(0);
case(fsm_state)
state1: begin
temp1=1;
simple_task(1);
end
state2: begin
temp1=0;
simple_task(0);
end
endcase
//////////////////////////////////////////////////////////
I am unable to understand which value will be assigned to temp1 and gbl_reg ?
Everytime the fsm_state changes, will temp1 and gbl_reg are assigned value 0. and depending on the fsm_state, temp1 and gbl_reg are assigned later.
Please read the code below and
//////////////////////////////////////////////////////////
reg gbl_reg ;
reg temp1;
task simple_task
input a;
begin
gbl_reg=a;
end
endtask
always@(*)
temp1=0;
simple_task(0);
case(fsm_state)
state1: begin
temp1=1;
simple_task(1);
end
state2: begin
temp1=0;
simple_task(0);
end
endcase
//////////////////////////////////////////////////////////
I am unable to understand which value will be assigned to temp1 and gbl_reg ?
Everytime the fsm_state changes, will temp1 and gbl_reg are assigned value 0. and depending on the fsm_state, temp1 and gbl_reg are assigned later.