primozb
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Hi,
I came across this **broken link removed** technology info (or Google for Tabula Spacetime routing). On link there is a nice video presentation explaining this new technology benefits.
I am working with HDL (Xilinx chips and tools) long enough, to learn that the major challenge of writing HDL code is to make "working HDL code” that “fits(!) in chip”. In other words: in simulations everything works OK very quickly, but then catching timing closures becomes a night mare.
Can anyone comment on this technology?
Is really that promising in solving timing closure problems as it is described?
WBR Primozb
I came across this **broken link removed** technology info (or Google for Tabula Spacetime routing). On link there is a nice video presentation explaining this new technology benefits.
I am working with HDL (Xilinx chips and tools) long enough, to learn that the major challenge of writing HDL code is to make "working HDL code” that “fits(!) in chip”. In other words: in simulations everything works OK very quickly, but then catching timing closures becomes a night mare.
Can anyone comment on this technology?
Is really that promising in solving timing closure problems as it is described?
WBR Primozb