I have stuck for 5 days, can anyone give me an idea?
The situation is
Eight 1-bit input ports a1~a8,
One 4-bit input port B, represents number 1~8
An table is consisted of 128 1-bit-registers,and numbered as 1~128,their initial value are given randomly
Eight 8-bit output ports,c1~c8
The scenario is
Among a1~a8,supposed there are 3 input ports a1 a4 a6=1,others are 0, and the input port B=2
My module should find 3*2=6 "0-value registers" from reg1 to reg128, supposed they are r2,r3,r5,r7,r11,r13(the rest 0-valued registers are ignored)
Then output the distributed register number
c1=2, 3 (in 2cycles)
c2=0,
c3=0
c4=5,7(in 2cycles)
c5=0
c6=11,13(in 2cycles)
c7=0
c8=0
and the used register should update to 1 before next searching
Can someone give me an idea about "HOW TO FIND THE VARIABLE NUMBER OF REGISTERS" in Verilog?
And can it implement in less than 8 cycles?
Thanks