SystemVerilog Tasks - Sequential?

I have a question about the order in which code will execute.

1 task reset();
2 ##[1:5] my_io.cb.rst <= 1'b1;
3 ##1 my_io.cb.rst <= 1'b0;
4 my_io.cb.iValid <= 1'b1;
5 my_io.cb.iCommand <= `PUSH_CMD;
6 my_io.cb.iData <= DEAD_BEEF;
7 ##[1:2] my_io.cb.rst <= 1'b1;
8 ##1 my_io.cb.rst <= 1'b0;
9 endtask: reset

What I believe will happen is things will be sequential, meaning line 2 will execute after a delay of between 1-5 clock cycles.
Following which there will be another clock delay, which is when line 3 will execute.
Line 4 will then execute FOLLOWED by line 5 and line 6. And so on...

I am not sure about this because the other way things could happen is:
Line 2 will execute after a delay of between 1-5 clock cycles.
However, independent of line 2, line 3 will execute after 1 clock delay (meaning it could execute before line 2.
On clock 0, line 4 5 6 will execute.

I guess my uncertainty comes from a lack of understanding of when/where/why or even if things are executed sequentially in SystemVerilog.

- - - Updated - - -

Okay so I found this online:

Classic Verilog has two ways of grouping statements - with a begin...end or fork...join. Statements
in a begin...end run sequentially, while those in fork...join executes in parallel and the statements within
the fork...join block has to be finished before the rest of the block can continue.

Click to expand...

Therefore, is this saying all SystemVerilog code runs sequentially unless it's in a fork...join?
So then if I had code as follows:

<stuff>
fork
begin
foo()
boo()
coo()
end
begin
doo()
end
join

would foo, boo, coo, doo run in parallel or would foo and doo run in parallel, then once foo finished boo, then coo, then doo?

Also, I thought verilog and systemverilog were basically the same. And I know that if I have:

always @(posedge clk)
begin
a <= 1;
b <= 2;
c <= 3;
d <= 4;
end

All those statements execute in parallel. So I'm super confused why would SystemVerilog be different, or is it a matter of context? If it is context, in which context is it parallel or sequential?

SystemVerilog is 100% backward compatible with Verilog, with the sole exception being reserved keywords.

The ##[1:5] syntax is not legal in SystemVerilog. Where did you see it?

A fork/join and begin/end block are both single statements that may contain 0 or more nested statements. The only difference is that the nested statements in the fork/join execute in parallel, while the nested statements in the begin/end execute sequentially. Your fork example above contains 2 statements, both begin/end blocks. The 2 begin/end blocks start in parallel, so foo() and doo() start executing in parallel. The join happens after both coo() and doo() finish.

The statements inside the begin/end block that go with the always construct also execute sequentially. But since these statements are non-blocking assignments, the updates to the left-hand side of the assignments are scheduled later. There is a lot of material on the internet about nonblocking assignments.