[SOLVED] SystemVerilog structure as a net

Hi all,
does anybody know whether it is possible to declare a structure in SystemVerilog as a net?
It is written in the book SystemVerilog for Design, 2-nd edition, by Sutherland, Davidmann and Flake, p. 97, but I did not find any notice of it in the Language Reference Manual. Maybe, it could be a suggestion or proposal that did not pass?
Thank for reply in advance.

In fact you can declare a net as a having structure data type. By default, all nets have the logic data type, which represents a single bit.

Are you reading the latest LRM? See section 6.7.1 Net declarations with built-in net types.

Thanks, Dave, indeed, the example in section 6.7.1 confirms that a structure can be declared as a net in SystemVerilog. However, this example seems to me as rather hidden, I think more suitable place for it would be in the section dealing with structures, e.g. 7.2, where I originally tried to find somethig like this.

Could you (or anybody else) please suggest me a purpose of such declaration, why it could be better or more suitable than simply a declaration of a structure without explicit wire specification, therefore with variable inferred? I am writing a textbook for students and I would like to give such suggestion in the textbook, nevertheless, I cannot get on a proper example or a purpose of such specification.

To better clarify my consideration - Example of declaration in LRM section 6.7.1 (page 62), structure declared as wire:

wire struct packed { logic ecc; logic [7:0] data; } memsig;

The same structure without wire specification, therefore declared as a variable:

struct packed { logic ecc; logic [7:0] data; } memsig;

dave_59 said:

In fact you can declare a net as a having structure data type. By default, all nets have the logic data type, which represents a single bit.

Are you reading the latest LRM? See section 6.7.1 Net declarations with built-in net types.

Click to expand...

Yes, this is an area that we (the IEEE 1800 committee) did not do a very good job when we merged the Verilog 1364 and SV 1800 LRMs. You have to realize that a data type is distinct attribute of a wire or variable.

When you do not use the wire specification, there is an implicit var specification.

var struct packed { logic ecc; logic [7:0] data; } memsig;

The var keyword means that the structure data type is being applied to a variable declaration. This implicitness was needed for legacy Verilog so that

reg A;

is implicitly

var reg A;

and

wire A;

is implicitly

wire logic A;


The reason you would want to apply a struct data type to a wire declaration is no different from the reason you would want to apply a struct data type to a variable -- you want a structured way to select parts of the wire or variable by identifier name instead of selecting numeric indexes.