systemverilog question on "&"

[layowblue]

for example:

logic [7:0] vector_a;
logic         bit_b;
logic         bit_result;
assign vector_a  = 8'h20;
assign bit_b       = 1'b1;
assign bit_result = vector_a & bit_b;

I understand this is not a good coding style. But I'm just curious about the result.
Cadence NCSIM shows bit_result is 1'b0;
Does Systemverilog has a clear say about whether the higher bit of the vector_a should be totally ignored in bit_result calculation?

Thanks

 

[kvingle]

Hello,

what you are doing with '&' is bitwise and operation. It operates on individual bits of one variable in expression and that of other variable.
To understand how it works I modified your example as below:

logic [7:0] vector_a;
logic [1:0]bit_b;
logic [1:0]bit_result;
assign vector_a = 8'h20;
assign bit_b = 1'b1;
assign bit_result = vector_a & bit_b;

now what last line does is

bit_result[0] = (vector_a[0]) and (bit_b[0])
and
bit_result[1] = (vector_a[1]) and (bit_b[1])

now in your case size of bit_result is only one bit hence only last 0th bit of vector_a is used in logical operation '&' with 0th bit of bit_b. Since this is 'bitwise and' it will work on individual bits. what you might need is '&&' which is logical and which operates on entire variable.

 

[ads-ee]

for example:

logic [7:0] vector_a;
logic         bit_b;
logic         bit_result;
assign vector_a  = 8'h20;
assign bit_b       = 1'b1;
assign bit_result = vector_a & bit_b;

I understand this is not a good coding style. But I'm just curious about the result.
Cadence NCSIM shows bit_result is 1'b0;
Does Systemverilog has a clear say about whether the higher bit of the vector_a should be totally ignored in bit_result calculation?

Thanks

kvingle explained the "&" operation.

To directly address your question about the bit_result calculation...

Even if you defined bit_b as:

logic [7:0] vector_a;
logic [7:0]bit_b;
logic bit_result;
assign vector_a = 8'h20;
assign bit_b = 8'hFE;
assign bit_result = vector_a & bit_b;

will also result in a bit_result of 1'b0, this is because vector_a & bit_b has a result of 8'b0010_0000. The assignment of this to bit_result ends up assigning only the red bit.

Assignments between differing widths results in either truncation of higher order bits or zero extending into the higher order bits.