Systemverilog OVM (Open Verification Methodology)?

[boardlanguage]

systemverilog ovm

Finally, it's here! (at **broken link removed**)

Can the Systemverilog experts tell us whether OVM will run on Synopsys VCS? And how does it compare to Synopsys VMM?

I bought the VMM Manual book, but I found it very difficult to understand. (I don't have a strong Systemverilog verification background.) The book-examples were complicated -- you have to get through a lot of testbench infrastructure just to do basic operations on the Device-Under-Test.

 

[mssajwan]

ovm vcs

Hi,
If you see the site it says
"The methodology is non-vendor specific and is interoperable with multiple languages and simulators"
So from this statement we can say it will work with VCS.
But personally I dont think so, stil we can not say much until we work out the OVM style on VCS.

2nd point here what i would like to mention here is, if you want to learn SV you dont need to know any methodology in particular. Take any simulator supporting SV and try out the different examples given in the tutorials. Jumping on the methodolgy starightaway is risky, u will end up loosing the enthu.
Just my personal views.

-Manmohan

 

[boardlanguage]

ovm systemverilog

I appreciate the feedback. I have played around with Xilinx Modelsim/XE 6.2c -- that was the only "free" Modelsim to support Systemverilog to a reasonable degree (for Design only, no SVA or advanced verification features)

My observation was that most of the 'verification methodologies' require a solid understanding of OOP (object-oriented programming), because they rely so much on class inheritance to partition testcases, BFMs, interconnect, randomization. In other words, the methodologies were developed by 'language experts' for use by other 'language experts.'

I'm going to download the OVM white-papers and see whether OVM is doable from a single-engineer's standpoint. (VMM definitely wasn't -- well not for me, anyway.)

 

[mssajwan]

ovm system verilog

Hi,
Well what i would suggest is if you have access to cadence, VCS or Mentors questasim u can start playing with examples.
secondly SystemVerilog requires knowledge of Verilog,then comes C++ even if you have basic knowledge of class concept that will work for you.So dont waste your time in getting a solid understanding of C++. You will get to know as you will progress,just a need basis.
Thirdly i would suggest don't get lost with methodology, OVM is a new one with support from Cadence & mentor but still at early stages.
so if u dont have access to any tool, download questasim from mentors, its a free 1 month support & start working towards SV.
Cheers!!
Manmohan

 

[boardlanguage]

ovm with vcs

Thanks again -- I've used Verilog-2001 for a while, and I played around with a simple Systemverilog design in Altera Quartus-II 7.2 -- so Verilog background is not a problem for me.

I'm confused about Questa. I thought Questa was a separate purchase, and you need to buy Modelsim/SE first? Or are you saying you can evaluate Questa if you already have Modelsim/SE? I've used Modelsim/PE, and the PE already has support for the design-constructs of Systemverilog -- no assertions or OOP stuff.

 

[aji_vlsi]

modelsim ovm

Hi,

I appreciate the feedback. I have played around with Xilinx Modelsim/XE 6.2c -- that was the only "free" Modelsim to support Systemverilog to a reasonable degree (for Design only, no SVA or advanced verification features)

That's a good starting point, but remember it is only SV-Design constructs that are supported there. So you have not rally played around with SV for Verification.

My observation was that most of the 'verification methodologies' require a solid understanding of OOP (object-oriented programming), because they rely so much on class inheritance to partition testcases, BFMs, interconnect, randomization. In other words, the methodologies were developed by 'language experts' for use by other 'language experts.'

I must agree with you - I went through the same pain few years back and that's when we (Ben, myself and Srini) decided to document the process of adopting VMM. You may want to take a look at: www.systemverilog.us and our book on Pragmatic Approach to VMM adoption . There are also several papers on VMM usage, see: solvnet.synopsys.com. We have 2 papers on that topic, I will be glad to share it with you if you drop me an email.

In general we find that once you master one methodology, the other ones are similar and hence easy to pick up.

I'm going to download the OVM white-papers and see whether OVM is doable from a single-engineer's standpoint

I certainly encourage that though I agree with other poster saying that OVM is still in its infancy and hence not many papers are out there.

. (VMM definitely wasn't -- well not for me, anyway.)

Well, if you care to - try our pragmatic approach book and let us know how it goes - it was intended to take VMM to every desktop

Cheers
Ajeetha, CVC
www.noveldv.com

 

[vishalvartak]

system verilog ovm

1) Understand different components in a TestBench viz. Stimulus_Generator (directed and random), Driver, Monitor, Scoreboard, Coverage_collector, Responder, Slave. Understand what they do and how to code them. If U try to code them for complex designs, U will understand the limitation of language like Verilog.

2) Now try to do the same thing using SystemVerilog (without going to OOPS concept or using classes). U will find that it is now much easier to code as compared to Verilog.

3) Now try to make all these components of TestBench as classes rather than modules. Understand how to pass unidirectional and bi-directional data between two classes (passing them between modules is very simple).

AVM or OVM is basically this third step + environment for connecting and running these components