Systemverilog "math_real" equivalent

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shaiko

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Hello,

VHDL has the "math_real" package.
This package has very useful functions such as trigonometrics, power, square root, etc...
Does Systemverilog have something equivalent ?
 

SystemVerilog has all these function built-in to the language, and not a separate package. See section 20.8.2 Real math functions in the IEEE 1800-2017 SystemVerilog LRM. Note that the power function is available as the operator x**y
 
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    shaiko

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Thanks dave_59,
Can the trigonometric functions be used in synthesis (during compile time) to setup values for constants ?
 

I don't see why not, but you'll have to check with your specific synthesis tool
 
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