SystemVerilog Calling Random Functions

I am trying to test a simple fifo design and would like to call various tasks (push, pop, pushpop) randomly.
How can I do that?

I'm new to Verilog and SV so please bear that in mind in the explanation.

Thanks

Look at the randcase and randsequence statements.

I want to take my question 1 step further. What if I want to add constraints?
Going back to my example, if I have a fifo and I want to randomize pushes, pops, and push_pops, however, I also want to ensure that I never pop when the fifo is empty?
I looked around online and found "constraint gaurds". But I was wondering if you could please check the sample code I made bellow and tell me if I'm understanding things right:


randcase
20 : push(data);
10 : constraint { if( fifo_io.cb.empty != null ) pop() } ;
50 : push_pop(data)
endcase

randsequence( main )
main : push := 20| pop := 10| push_pop := 50;
push: push(data);
pop: constraint { if( fifo_io.cb.empty != null ) pop() } ;
push_pop: push_pop(data);
endsequence


How does that look?

You cannot use constraints with these constructs - they are only for the built-in randomize() method. However, you can dynamically modify the weights; a weight of zero means that branch will not be taken.

There are a few other things you could do with the randsequence, like if-else productions, but I'll leave that as an exercise.