SystemVerilog Behavioral Simulation in Cadence Virtuoso/AMS/Incisive/Spectre

[Puppet123]

Hello,

I want to do behavioral simulations using SystemVerilog as opposed to using Verilog-A and Verilog-AMS for Mixed Signal Designs in Cadence Virtuoso/AMS/Incisive/Spectre.

How can I use SystemVerilog files ? Can I use them just as I use Verilog-A or Verilog-AMS files ? Will Cadence Virtuoso/Spectre/Incisive/AMS recognize SystemVerilog and just compile and simulate just as with Verilog-A and Verilog-AMS ? Are there any special considerations in using SystemVerilog with Cadence Virtuoso/Spectre/Incisive/AMS?

Thanks.

 

[pancho_hideboo]

https://designers-guide.org/forum/YaBB.pl?num=1574282166

Use file name of “*.sv”.

Surely understand basic things correctly before EDA Tool Play.
This is very true for all your previous posts.

 

[Puppet123]

I know what .sv is.

I am talking about analog / mixed signal simulation.