System Verilog: Virtual

no_mad · May 15, 2014

Hi,

I'm new in System Verilog with OOP.
Here is my question.

What's the motivation of "virtual" in SV OOP?
⇒virtual method
⇒virtual class

Can someone please explain this to me.
Why We need "virtual" ??

Please help me out here. Thanks

-no_mad

dave_59 · May 16, 2014

The virtual keyword is used for different but related purposes in OOP. Generally it means something you reference indirectly as if it were one type, but actually get back something else. In OOP, this concept is also refereed to as polymorphism. This is a big topic, but fortunately there is a lot of reference material on this around.

no_mad · May 17, 2014

Thanks Dave.

Now I can continue my journey to be System Verilog with OVM expert...my personal goal.
My first step is understanding OOP in System Verilog.

I read your article on classes. That is really good article.
Thanks

-no_mad

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