system verilog simulators?

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manchal

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Modelsim SE 6.3f has option for system verilog files,but does it support its testbenches and verification.?
Do we have free simulators for system verilog?
 

The free versions of ModelSim support all of SystemVerilog except assertions, randomize(), and covergroups. You will have access to all of SystemVerilog's object-oriented programming features to run basic UVM testbenches.

I'm not aware of any free simulators supporting the full SystemVerilog feature set. (And if I did know, I wouldn't tell you )
 
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