System Verilog Modelsim issue

Status
Not open for further replies.
V

Vaibhav Sundriyal

Newbie level 4
Joined
Jan 31, 2014
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
36
`timescale 1ns/1ps
Code Verilog - [expand]
1
2
3
4
5
6
7
8
9

module example(input logic a,b,c,output logic y);
 
logic ab,bb,cb,n1,n2,n3;
assign #1{ab,bb,cb}=~{a,b,c};
assign #2 n1=ab&bb&cb;
assign #2 n2=a&bb&cb;
assign #2 n3=a&bb&c;
assign #4 y=n1|n2|n3;
endmodule


The above code snippet assumes that inverters have delay of 1 ns, AND gates have delay of 2 ns and
OR GATEs delay of 4 ns. When I simulate this code in modelsim, it shows delay of 1 ns for ab,bb, and cb but delay of
4 ns for n1,n2 and n3? Why is it so? Shouldn't the delay be 2 ns.

Thanks
 
Last edited by a moderator:

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…