System verilog `include problem in vcs

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arjun1nh07

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Error-[SFCOR] Source file cannot be opened
Source file "fsm_trans.sv" cannot be opened for reading due to 'Not a
directory'.
Please fix above issue and compile again.
"../lib/fsm_env.sv", 3
Source info: `include "fsm_trans.sv"

I got the error while compiling with the command


vcs -lca -sverilog -Mupdate ../rtl/all_fsm_Mod_fin.v ../env/fsm_if.sv ../lib/fsm_trans.sv ../lib/fsm_gen.sv ../lib/fsm_drv.sv ../lib/fsm_receiver.sv ../lib/fsm_env.sv +incdir+../lib/fsm_trans.sv -debug_all +v2k

If anyone knows the solution please help me friends.
:-x:-x:-x:-x:-x
 

you probably mean: +incdir+../lib/
incdir points to the directory where vcs will search for included files
 

you are passing a file attribute to +INCDIR+ which is not true. use the directory instead.

+incdir+../lib

~Nandasan
 

guys, i'm not sure if this worked. But, i see the same problem
however, as suggested earlier, i'm doing the following:
+incir+../lib \
../lib/fsm_env.sv

does anybody have any suggestions?

Thanks
 

Basically it is not able to find the file in the path specified under +incdir. Check whether the file is present in the path.
 

haneet said:
guys, i'm not sure if this worked. But, i see the same problem
however, as suggested earlier, i'm doing the following:
+incir+../lib \
../lib/fsm_env.sv

does anybody have any suggestions?

Thanks
Click to expand...

I hope you are not make a typo! The compile option is "incdir" and not "incir".
 

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