Jun 16, 2015 #1 R russeree Newbie level 2 Joined Jul 14, 2013 Messages 2 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 11 I am very new to functions, I have a parameter to specify the input freq(mhz). Would this return a value I could use to specify a vector width? Code: function int _ms_unit_width; int freq_mhz = (int_input_freq_mhz/1000); _ms_unit_width = ($clog2(freq_mhz)+1); endfunction
I am very new to functions, I have a parameter to specify the input freq(mhz). Would this return a value I could use to specify a vector width? Code: function int _ms_unit_width; int freq_mhz = (int_input_freq_mhz/1000); _ms_unit_width = ($clog2(freq_mhz)+1); endfunction
Jun 16, 2015 #2 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,823 Reputation 3,656 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,209 Using $clog2 is how you do that in Verilog so it should work just as well in SV.
Jun 16, 2015 #3 R russeree Newbie level 2 Joined Jul 14, 2013 Messages 2 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 11 I was more concerned about the output type of an int? Is that a legal value to put a 'input wire [x:y] name' declaration?
I was more concerned about the output type of an int? Is that a legal value to put a 'input wire [x:y] name' declaration?
Jun 16, 2015 #4 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,823 Reputation 3,656 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,209 Verilog and sv aren't strongly typed languaages like VHDL, so you can assign an integer to a wire vector, though you may end up with truncation depending on the value of the integer and the width of the vector.
Verilog and sv aren't strongly typed languaages like VHDL, so you can assign an integer to a wire vector, though you may end up with truncation depending on the value of the integer and the width of the vector.