[SOLVED] system verilog forever loop

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sumeet1990

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1)
Code:
module enum_test;
 enum {red,green,blue,yellow} c;
 initial
 begin
 c=c.first;
 forever
 begin
 $display("%s %d",c.name,c);
 if(c==c.last)
 break;
 c=c.next;
 end
 end
 endmodule


2)
Code:
module enum_test;
 enum {red,green,blue,yellow} c;
 initial
 begin
 c<=c.first;
 forever
 begin
 $display("%s %d",c.name,c);
 if(c==c.last)
 break;
 c<=c.next;
 end
 end
 endmodule
3)
Code:
module enum_test;
 enum {red,green,blue,yellow} c;
 initial
 begin
 c<=c.first;
 forever
 begin
#10   //<<<<<-------------------things change by adding this
 $display("%s %d",c.name,c);
 if(c==c.last)
 break;
 c<=c.next;
 end
 end
 endmodule
Hello,
I am new to SV please help me with the codes above
1)In the first code I used forever loop with blocking assignments and with and timing procederals and everything works nicely.I get red,blue,green,yellow resp.

2)Int the second code I am using non blocking statements and while simulating it hangs the simulation by displaying "red","0"

3) in the third code I just added a delay and simulation works fine displaying values after specified delay

Now, I now the working of blocking and non blocking assignments but just can get how it is working in the above codes. also, I don't quite get how this delay addition affects the code.
thank you in advance
 
Last edited by a moderator:

thank you, that cleared my doubt in codes 1 and 2.
But can you please explain what exactly happens after we add delay....i mean can you give me a line by line explanation after addition of delay in third code
 

Now, I now the working of blocking and non blocking assignments
sharath666 is correct and you don't know about blocking and non-blocking statements as well as you think you do. ;-) You should probably reread the LRM 4.9.3 Blocking assignment and 4.9.4 Nonblocking assignements sections of the IEEE Std 1800-2012 to improve your understanding of how each of them work.
 
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