[SOLVED] System verilog extended class and constrained random question

Code Verilog - [expand]
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// Code your testbench here
// or browse Examples
class packet;
  rand byte data[];
  rand bit [7:0] length;
  
  constraint payload_size_c { data.size inside { [1 : 250]};}
  
endclass
 
class gen;
  rand packet pkt;
  function exec();
  pkt = new();
  if ( !pkt.randomize()) $fatal("Gen: trans randomization failed");
  endfunction: exec
endclass
 
class small_packet extends packet;
 
  constraint small_c { data.size < 10 ; }
endclass
program test;
  small_packet spkt;
  gen sgen;
  
  initial begin
   spkt = new();
    sgen = new();
    sgen.pkt = spkt;
    sgen.exec();
        
    $display("Size = %d, length = %d",sgen.pkt.data.size,sgen.pkt.length);
    
  end
endprogram