System verilog Compilation error

Thread starter Sindhiya C R
Start date Oct 17, 2013

Status: Not open for further replies.

Oct 17, 2013

Sindhiya C R

Newbie level 4

Hi,
We can use typedef inside the class for include another class. I am having class as base,and interface as network and I have instantiated this interface inside the base class..While compiling this base class it showing error in interface instantiation
I tried as below..But it shows error only

//Interface
interface network();

//input/output

modport mod(cb)
endinterface

//BASE class
typedef network.mod intf;
class base;
virtual interface network.mod intf;
endclass

or any other way to avoid compilation error while compiling this base class with interface?

Status: Not open for further replies.

Similar threads

E
Which one should I learn today? Verilog or Systemverilog?
- Started by electronicslab
- Oct 27, 2024
- Replies: 2
PLD, SPLD, GAL, CPLD, FPGA Design
E
Which simulator should I use for verilog?
- Started by electronicslab
- Oct 26, 2024
- Replies: 9
PLD, SPLD, GAL, CPLD, FPGA Design
I
1st order sigma delta output is wrong verilog Cadence
- Started by InvokeMeWell
- Sunday at 7:52 PM
- Replies: 4
PLD, SPLD, GAL, CPLD, FPGA Design
E
Is there anything that converts verilog to resistor, capacitor level design?
- Started by electronicslab
- Oct 27, 2024
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design
E
The reason of Verilog signed math calculation error
- Started by EDA_hg81
- Sep 17, 2023
- Replies: 4
PLD, SPLD, GAL, CPLD, FPGA Design

System verilog Compilation error

Sindhiya C R

Newbie level 4

Similar threads

Privacy & Transparency

Privacy & Transparency