System Verilog Assertions.

Thread starter mys.rahul
Start date Jan 6, 2015

Status: Not open for further replies.

Jan 6, 2015

mys.rahul

Newbie level 1

Hi,

I am writing assertions for some of the sequences. I want to update a register after an assertion is covered and use the register value to CROSS with an other register value, Can you please guide me on the implementation of the above problem statement.

Thanks,
Rahul

Status: Not open for further replies.

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System Verilog Assertions.

mys.rahul

Newbie level 1

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