system verilog assertions

anudeepzip@gmail.com · Jul 20, 2012

assert (bad things do not happen)
cover(good things happen)
then what is the difference between assert and cover .y do we use both
from above it seems to be same

jasonc2 · Jul 25, 2012

See: http://www.asic-world.com/systemverilog/assertions21.html
And: http://www.testbench.in/AS_08_VERIFICATION_DIRECTIVE.html

Assert would be used to check that conditions that should be true actually are true, and fails immediately if the conditions are false.

Cover is used to check conditions but rather than acting immediately, the conditions are checked and a report can be generated at the end.

system verilog assertions

anudeepzip@gmail.com

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jasonc2

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system verilog assertions

anudeepzip@gmail.com

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