System Management Wizard 1.3 for Zynq Ultrascale+ Over Temperature (OT) not working as intended

[Beginner_in_FPGA]

Hey all,

I have setup a design in the xczu19eg FPGA which contains PCIe, QSFP and some DMA.

To implement Over temperature protection, I have used the System Management Wizard IP to enable OT and have configured the same for trigger and reset (Hysteresis mode).

When the board reaches the Trigger temperature it shuts down it's operation as intended. But when the temperature decreases below Reset temperature it doesn't show any indication of startup sequence being run, even after keeping it on for a very long time.

Does the IP actually allow this feature of restart after the temperature decreases by itself, or should I enable something else in the design. I am asking this because to enable shutdown I had to configure the xdc file with -

"set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]"

So do I have to do a similar thing for Reset of OT.



Thank you,

Best Regards.

 

[dpaul]

Does the IP core documentation say anywhere that it can power-up the FPGA?
If not then it possibly cannot!
You have to think of other mechanisms in that case....

 

[Beginner_in_FPGA]

Hey dpaul,
In the IP Core documentation they have mentioned contradicting statements as far as I see.
"when the die temperature exceeds the OT upper threshold (or the default of 125°C), the OT alarm logic output becomes active and 10ms later the device initiates a shutdown sequence. When the automatic shutdown starts, the device is disabled and GHIGH is asserted to prevent any contention (see the UltraScale Architecture Configuration User Guide (UG570) [Ref 4]. When OT is deasserted (50°C as shown in Figure 4-4), GHIGH is also deasserted and the start-up sequence is initiated releasing all global resources." - This statement supports start-up.
also
"The automatic shutdown feature is intended to prevent permanent damage to the device. After the temperature has gone below the OT lower (57h) setting and OT is deasserted, the device should be reconfigured to ensure the device is reset to a known safe state." - This statement tells us to reconfigure the FPGA after shutdown occurs.
I am confused by the same and was wondering if anyone here has experience in this feature of the IP Core.
Any help would be greatly appreciated.

Reference - https://0x04.net/~mwk/xidocs/ug/ug580-ultrascale-sysmon.pdf (page 91, 92, 93 & 94)
https://docs.amd.com/v/u/en-US/pg185-system-management-wiz

 

[dpaul]

@Beginner_in_FPGA
I have never used this IP core so do not take my asnswers as a certain.

But if "the device should be reconfigured to ensure...." means the bitstream from external Flash needs to be loaded, then I would guess the same thing should occur as when you first power up the FPGA.

Why do you not try it out. Make the FPGA die temperature go high and observe the FPGA shut-down, after that use a coolant spray over the FPGA to bring the die temp down. Then bbserve what happens.

Also put this question to the AMD FPGA support forum and see what the official reply is.

 

[Beginner_in_FPGA]

Hey @dpaul

Make the FPGA die temperature go high and observe the FPGA shut-down, after that use a coolant spray over the FPGA to bring the die temp down. Then bbserve what happens.

Yes, I tried doing this. As temperature hits the upper limit of shutdown the board shuts down, but after the board cools down it doesn't boot up by itself.
But when I cold/warm reboot the entire system, without having to flash the board with a fresh image it boots up and runs as if nothing happened.

I think this is the maximum the IP offers and it might not support self startup as it seems.
Will be still testing what can be done and will get back to you if I ever get a solution on the same.

I posted this question in the AMD FPGA support forum and didn't get a reply, hence I'm out here.