system level simulation and design question

[nijMcnij]

hello all,

i am about to start work on an charge redistribution SAR ADC, however, i would like to do the so called system level simulations in Matlab/Simulink.

can someone please shed some light on this matter, maybe provide a reference also.

many thanks

 

[Syukri]

firstly u need to really understand the architecture...

Then every component in SAR need to drawn a block....the comparator, DAC and S&H ciruit.

I beleive in MAtlab all these block has already there....Sample and Hold is under sample circuit

Connect them all. double click on the block...and play with the parameter untill u achieve your spec...

Use that value as a guideline when u go down to the transistor level then....

 

[nijMcnij]

thanks suykri for your reply,

unfortunately , i was told to conduct the system level simulation using verilogA.

i know a bit about verilog, and i checked the cadence verilogA reference guide, the syntax is the same, but yet i am a bit clueless as to how to simulate capacitors and resistors and transistor switches.

do u have a nice tutorial with some worked examples to get started on this thing?

many thanks