ombadei
Member level 3
systemc verilog
Hi,
I've been tasked by my supervisor to interface from System C to Verilog.. I have just been introduced to these tools.. So, i am not sure on what exactly I must do to set the infrastructure up..
But basically, i need to simulate a RAM controller (SystemC) to the timing diagrams of Micron's RAM simulation model (Verilog).
Anyone has any elaborative insights about doing so?
Thanks.
Hi,
I've been tasked by my supervisor to interface from System C to Verilog.. I have just been introduced to these tools.. So, i am not sure on what exactly I must do to set the infrastructure up..
But basically, i need to simulate a RAM controller (SystemC) to the timing diagrams of Micron's RAM simulation model (Verilog).
Anyone has any elaborative insights about doing so?
Thanks.