Sysnthesis of Constants in VHDL

[Karandeep]

Hello Everyone,

I want to know the what is the circuit equivalent of CONSTANTS in VHDL. While designing in frontend we always have in our mind how the code would be synthesized , what part of the code would corresponds to FF, what to LATCH, what to gate nad so on. But I cant understand what would be equivalent to CONSTANT.

One of my friend suggested me that it would become a wire equivalent connected to VDD or GND depending upon the value of constant. But this feds me up why we use these overheads for wires, insted if condsidering this would become equivalent to ROM(Fuse based, etc). Then do we consider it as ROM or seprate wires connceted to VDD or GND.


Hope to see replies soon. Thanks in advance

 

[yx.yang]

For constant nets, they can be connected to VDD/VSS.
But for ESD issue, the cell library usually exit cells name "TIELO"/"TIEHI" (tie low and tie high).

 

[Karandeep]

For constant nets, they can be connected to VDD/VSS.
But for ESD issue, the cell library usually exit cells name "TIELO"/"TIEHI" (tie low and tie high).

Hello yx.yang,

how this is structure is different from structure of ROM?. ROM is also a net connected to VDD-VSS, this nets connection would them be called "A ROM without address directly connected to the hardware without read/write ... nad others signals. It would be a ROM with only data lines with a kind of selector pin decided by hardware."

Consider it from harware point of view.

 

[FvM]

Your question is incomplete. There are different kinds of constants which will synthesize differently. A simple constant input to a logic expression will be represented by a wire in RTL. But in synthesis, it's propagated into the logic and possibly causes a constant logic output, removing one or more logic elements. If you are talking about ASICs, there won't be a single superfluous gate with constant input, except for output drivers or elements created at will. In FPGA synthesis, you'll find many logic elements with constant input after mapping the design to gate level, but not necessarily the same as in the RTL description.

On the other hand, there are things like constant arrays that will be synthesized as ROM tables.

 

[Karandeep]

Your question is incomplete. There are different kinds of constants which will synthesize differently. A simple constant input to a logic expression will be represented by a wire in RTL. But in synthesis, it's propagated into the logic and possibly causes a constant logic output, removing one or more logic elements. If you are talking about ASICs, there won't be a single superfluous gate with constant input, except for output drivers or elements created at will. In FPGA synthesis, you'll find many logic elements with constant input after mapping the design to gate level, but not necessarily the same as in the RTL description.

On the other hand, there are things like constant arrays that will be synthesized as ROM tables.

Hello FvM,

Thanks for your replies, but I need some more detailed answer , for that sure, I have to elaborate my question.

Actually I am going to implement an algroithm SHA which is for cyrpotogrphy. Now thw alogrithm needs some constant values (64+8=72), so i was thinking that if i need to implement this I simply declare a constant and assigns its value to the required the register. Now conversly thinking of the fact that if these constants would be a bunch of wires, how these bunches are different form ROM cells. This is really confusing me a lot. If I thought from post layout point of view , it resembles the ROM.

So , my query is these constants would become a ROM cell after synthesis.

Actually , I am intersted in post synthesis results.

 

[FvM]

There are prerequisites for ROM inference, generation of FPGA internal ROM from HDL code. With most FPGA families, ROM is synchronous, the constant data must be assigned under a clock edge sensitive condition. As an example, a case construct, that assigns different values to signal for each round in SHA1 code will usually infer a ROM, if it's in a clock edge sensitive process.

 

[Karandeep]

There are prerequisites for ROM inference, generation of FPGA internal ROM from HDL code. With most FPGA families, ROM is synchronous, the constant data must be assigned under a clock edge sensitive condition. As an example, a case construct, that assigns different values to signal for each round in SHA1 code will usually infer a ROM, if it's in a clock edge sensitive process.

Hello FvM,

Thanks a lot . Now I am trying to get the point . I would like to know for instance of SHA, the values for default Kt and H(i)(default hash values) should be taken as constant or stored in ROM(specific to SHA).

Another question , what would be the deciding factor for choice between ROM and CONSTANTS.

 

[FvM]

I expect that a ROM implementation is preferable to save FPGA resources. In a reasonable synchronous design, the design compiler will be able to generate ROM for constant tables and case constructs with constants automatically. As an example, you can refer to the SHA cores from opencores.org.

 

[Karandeep]

I expect that a ROM implementation is preferable to save FPGA resources. In a reasonable synchronous design, the design compiler will be able to generate ROM for constant tables and case constructs with constants automatically. As an example, you can refer to the SHA cores from opencores.org.

I have gone through the code and found that the constants are used instead of ROM.

Q1. This again arises a question in my mind that from RTL designer point of view , the designer is only concerned with the use of constants, rest depends upon the complier that how it could be synthesized ??? It is so.

Q2. The constants used in code would then be broadly called as ROM.??

`define SHA256_H0 32'h6a09e667
`define SHA256_H1 32'hbb67ae85
`define SHA256_H2 32'h3c6ef372
`define SHA256_H3 32'ha54ff53a
`define SHA256_H4 32'h510e527f
`define SHA256_H5 32'h9b05688c
`define SHA256_H6 32'h1f83d9ab
`define SHA256_H7 32'h5be0cd19

`define K00 32'h428a2f98
`define K01 32'h71374491
`define K02 32'hb5c0fbcf
`define K03 32'he9b5dba5
`define K04 32'h3956c25b
`define K05 32'h59f111f1
`define K06 32'h923f82a4
`define K07 32'hab1c5ed5
`define K08 32'hd807aa98

are given in the the refrence example.

 

[FvM]

I have gone through the code and found that the constants are used instead of ROM.

Yes, that's what I said.
Q1+Q2: You should check if the constants are implemented as intended. It's a way of describing ROM hardware.

 

[Karandeep]

I have synthesized the design with XILINX ISE and the constants became LUK-UP-TABLES...........