[SOLVED] synthesizing without I/O in vivado

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BartlebyScrivener

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I have a design which is to be integrated into other designs on an FPGA. I would like to see how it performs in isolation (clock speed/size etc). If I try to synthesise, obviously as no inputs/outputs are assigned, vivado just clears all the logic as it does nothing. How can I get vivado to pretend there might be inputs without assigning all my i/o to pins?

I hope that makes sense!

Thanks.
 

I know its easily done in Altera Quartus with the virtual pin assignment.
But from experience from other engineers, the same thing was not possible in ISE. Whether it's been added to vivado, I dont know, but a quick google doesnt reveal any promising results.

The only suggested options are to just leave all the pin assignments blank, and let vivado auto-assign pins. If there are not enough pins, pick a larger device.
 
Thanks. My design is a network, it has thousands and thousands of pins, I am going to need an impressive device! I believe Altera won't let me use virtual pins on a student license unfortunately. Oh well!
 

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