Synthesizing a very simple two-state FSM (Moore machine) with ISE results in the following schematic. Thing is that the 2-LUT has no control input. So, it is not clear for me, how that LUT work actually. Is there something messing?
Without supplying the code you synthesized nobody can say if the LUT is correct or not. Though based on your description it probably is correct.
There is one input to the FSM from an external pin and the output of the FSM is fed back to the LUT. So unless you are saying you have 2 or more inputs to the FSM and you only have one showing then there isn't anything wrong.
FYI, A 2-input LUT (look up table) can produce any function of those 2 inputs. Including the state transitions for a s0-s1 state FSM.
Your design does only need 2 inputs: X and current state. the state will be encoded as a single bit as it only has 2 states. So the RTL diagram in your first post is exactly as I would expect.
I know it is correct, but I don't know why the LUT in the diagram has two inputs. As I said and based on what we have learned, a 2-LUT has 3 inputs as I show in my previous post. If you insist that the diagram is OK, then please write the boolean equation of the D (input flip flop)
TrickyDicky, that is not an AND gate. It is an XOR gate. To be sure, I synthesized the same code with Quartus and gave me better understanding. Please see the picture.
If one wants to put a 2-LUT instead of an XOR gate, he has to do like this
Code:
+-----+
| |
X ----- | |
| |--------D
X'----- | |
| |
+-----+
|
+------ Y
But I dont' see such thing in the ISE's output. The ISE feeds X (input only) and Y without any control input. Still I think the ISE's output is vague
I really dont understand what you're getting at? ISE and Quartus have produced the same circuit. IE. Y' is dependent on Y and X only ie. 2 inputs.
I dont understand by what you want with some imaginary C input? using X, X' and Y would give you a 3 input LUT.
Ah, that makes sense...the two input LUT contains a mux to select the FSM branch taken and the resulting next state.
Though the OP doesn't seem to understand that the two bits being muxed are both state bits with the X input selecting between SA or SB states, which just so happens to be cu_state or NOT cu_state.