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+-----+
| |
a1----- | |
| |-------- y
a2----- | |
| |
+-----+
|
c-------+
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 library ieee; use ieee.std_logic_1164.all; entity fsm is port( x, clk, rst: in std_logic; y: out std_logic); end; architecture x of fsm is type state is (SA, SB); signal cu_state, nx_state: state; begin process(clk, rst) begin if rst = '1' then cu_state <= SA; elsif (clk'event and clk = '1') then cu_state <= nx_state; end if; end process; process(x, cu_state) begin case cu_state is when SA => y <= '0'; if x = '0' then nx_state <= SA; else nx_state <= SB; end if; when SB => y <= '1'; if x = '1' then nx_state <= SA; else nx_state <= SB; end if; end case; end process; end;
+-----+
| |
X ----- | |
| |--------D
X'----- | |
| |
+-----+
|
+------ Y
As I said and based on what we have learned, a 2-LUT has 3 inputs as I show in my previous post.
a b | c
-----+-------
0 0 | f(0,0)
0 1 | f(0,1)
1 0 | f(1,0)
1 1 | f(1,1)
He is confusing LUT with MUX. Look in post #1 what is the name of the LUT: MmuxYour instructor is misleading you if this is what you were told...
A two input LUT does this
He is confusing LUT with MUX. Look in post #1 what is the name of the LUT: Mmux