Synthesizing VHDL code of a PLL

[ahmad_abdulghany]

Hi,
Simple question,
Can a complete PLL (digital) be synthesized from a VHDL or Vrilog code?
I mean the structural level not only behavioural one!
Is that case practical?
Thanks in advance,
Ahmad,

 

[khaila]

pll vhdl

Hi,
Simple question,
Can a complete PLL (digital) be synthesized from a VHDL or Vrilog code?
I mean the structural level not only behavioural one!
Is that case practical?
Thanks in advance,
Ahmad,

Salam 3alikom,

Actually PLLs has Analog circuits which mean that the sunthesizrs could not treat i as digital hardware completly.
Generally, PLLs are included in the ASIC library vendors. It supplies SIMULATION models.

In FPGA worlds:
You may use the PLLs of the vendor, XILINX or ALTERA...
They also supplies BLACK BOX models which immulate PLLs.
That BB are modelated in VHDL or VERILOG so you can modefied its parameters, then the simulator or the synthesizer will take care very well for these parameters.

Configuration of the PLL's paramaters should be modified at the power-up of the IC. You will not be able to change in real-time.

خليل عبد الرحيم