xiongdh
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synthesizing three-state disabling logic?
from the scan synthesis user guide v2000.05,it is said" To prevent bus contention or bus float,internal three-state nets in your design must have a single active driver during scan shift. DFT Compiler automatically performs this task."
but by do the exercise :Testability at the Module Level in Test Automation Tutorial of sold.a three-state output driver was added a control signal test_se by command insert_scan.and in the scan shift mode, the signal test_se='1' shut off the three-state driver.the bus have no other driver and have no pull-up or pull-down,so it is a bus float in shift mode.This is conflict with the above sentence but no error report by command check_test and create_test_patterns -dft .Why???????
from the scan synthesis user guide v2000.05,it is said" To prevent bus contention or bus float,internal three-state nets in your design must have a single active driver during scan shift. DFT Compiler automatically performs this task."
but by do the exercise :Testability at the Module Level in Test Automation Tutorial of sold.a three-state output driver was added a control signal test_se by command insert_scan.and in the scan shift mode, the signal test_se='1' shut off the three-state driver.the bus have no other driver and have no pull-up or pull-down,so it is a bus float in shift mode.This is conflict with the above sentence but no error report by command check_test and create_test_patterns -dft .Why???????