Hi
For Synthesizing a RTL to netlist using either Synopsys DC or Cadence RC, we need
Technology libraries => which has cell complete information.
Symbol Libraries => cell schematic information
Constraints File => various delays, clock definitions specified.
Please tell how does these Tech and Symbol files being generated.
To me, these library are developed by Backend people (basically Library development team). They develop the layout using layout-editor and analyze the cell parasitics using tool and the output is
generated as file called technology file and symbol library.
Now these are given to Compiler which uses constraints and map the library cells to the RTL blocks and come up with the file where RTL information has been transformed into cells level information
having delays incorporated.
Please put your thoughts and correct my perception if wrong.
Nitint08