erik_xfan
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Hello, everyone:
We encountered a problem on specifying clock signals in DesignCompiler (DC) for synthesis.
Our RTL design is fully synchronous, triggered by only one input clock. For some reasons, we have to partition the design into a number of blocks, and to synthesize each block with a local clock. All the local clocks are the same in frequency as the input clock, but with different phase shifts. In CTS the layout tool will then generate a global clock, which has the inter-block clock-tree latency as defined by synthesis.
In brief, we need to synthesize a synchronous design, while with a group of mesochronous clocks. Any modification on the RTL codes, like adding input clocks, is forbidden.
The challenge seems to specify a clock, which on different blocks has particular clock phases. Is this possible in DC? Does anyone has the experiences on this topic? Any suggests or comments are highly appreciated!
We encountered a problem on specifying clock signals in DesignCompiler (DC) for synthesis.
Our RTL design is fully synchronous, triggered by only one input clock. For some reasons, we have to partition the design into a number of blocks, and to synthesize each block with a local clock. All the local clocks are the same in frequency as the input clock, but with different phase shifts. In CTS the layout tool will then generate a global clock, which has the inter-block clock-tree latency as defined by synthesis.
In brief, we need to synthesize a synchronous design, while with a group of mesochronous clocks. Any modification on the RTL codes, like adding input clocks, is forbidden.
The challenge seems to specify a clock, which on different blocks has particular clock phases. Is this possible in DC? Does anyone has the experiences on this topic? Any suggests or comments are highly appreciated!