tanish
Junior Member level 2
I have a problem synthesizing my design.
Its submodules can be synthesized however when I want to synthesize the top module, Genus doesn't finish the elaboration.
But there are no errors, because I check it with Modelsim to see if there is any. Also by reading the HDL file in Genus I don't receive any error.
I have used several arrays in my design which are very huge.
like: reg [31:0] mem [0:500000]
I set the attribute hdl_max_memory_address_range in order to increase the max size of interpretable memory size for genus but after one week the elaboration has not finished yet!
Can anyone help me with this?
Its submodules can be synthesized however when I want to synthesize the top module, Genus doesn't finish the elaboration.
But there are no errors, because I check it with Modelsim to see if there is any. Also by reading the HDL file in Genus I don't receive any error.
I have used several arrays in my design which are very huge.
like: reg [31:0] mem [0:500000]
I set the attribute hdl_max_memory_address_range in order to increase the max size of interpretable memory size for genus but after one week the elaboration has not finished yet!
Can anyone help me with this?