just few notes
you can guide the tool to focus on reducing resource usage
[if possible] with the following settings:
Code:
settings ->
Analysis & Synthesis ->
Optimization Technique : Area
More Settings... ->
Auto Resource Sharing ON
Remove Duplicate Reg ON
Remove Redundant Logic ON
Compilation Process Settings ->
Optimize for fitting: check both options
you can find if you have unwanted latches by grep the map report
for strings: "inferring latch" and/or "inferred latch"
[ btw. latch itself is not bad if you do it intentionally and
you can explain why you use it... ]
synchronizing the design will not reduce area, you will get
the same combo gates number plus registers,
what you can gain is possibility of re-use one module/block
then having two or more the same blocks in parallel
[e.g instead of having 2 multipliers doing a*b and c*d,
you can have one with a mux in front of it, not always
applicable of course]
your design does not use memory, in fact all gates in fpga
are look-up tables, i.e small memories, you can quite effectively
use internal fpga ram as a 'logic generator', decoders etc.
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have fun