[SOLVED] Synthesize SRAM compiler output in verilog

[kyonglee]

Hello,

I am using artisan sram compiler and could get verilog view for my sram. I am trying to synthesize the sram with some glue logic using design compiler, but failed because the verilog code for sram is not synthesizable. I have tried to generate everything that I can generate from the sram compiler, but the only files that might be relevant to design compiler is the verilog code and .lib files.

Is there any way that I can synthesize sram from sram compiler? Any comments and links are good and step by step instructions are better.

Thanks!

 

[jiancongwoo]

1. using library compiler convert lib file to db file
2. add the db file to your dc synthesis scripts, like "set link_library [concat $link_library $your_mem.db]

done !

 

[kyonglee]

Thank you!!
I didn't include .v file from my sram compiler but do include .db file.
Design compiler consider my sram as a black box, so there is no sram synthesized in my gate level netlist, but timing report contains sram timing information.
This is exactly what I want.

 

[jiancongwoo]

Thank you!!
I didn't include .v file from my sram compiler but do include .db file.
Design compiler consider my sram as a black box, so there is no sram synthesized in my gate level netlist, but timing report contains sram timing information.
This is exactly what I want.

%dc_shell> check_design
to check there are any unresolved module, if yes. check your search_path
you need to add Memroy Verilog top module(only input & output port information) to you Design