Hi all,
I have a verilog structural net list that, besides having all sorts of logic gates and ffs, it has a number of macros described as timing models by a separate *.lib and *.lef files.
Functions represented by our macros are complex sequential functions. Too complex to be put into the *lib files. So we cannot describe them as cells. However, since all the delay, power and timing attributes are present in the *.lib file, RC/Encounter recognize these pieces as "timing models".
Moreover each of these macro have a variety of drive strengths. We designed and characterized such macros and named them appropriately, pretty much like:
MACRO1X4
MACRO1X8
...
MACRO2X4
MACRO2X8
...
and so on. Every macro for every size has lib file entry with full timing/power specification extracted from characterization runs.
QUESTION:
I was expecting the synthesizer to automatically pick up sizes base on name pattern matching, however it does not seem to happen.
Is there any way to tell synthesizer that macros represented as "timing models" come in different sizes?