I have a requirement of synthesizing an RTL code in which, some of the gates should be synthesized from a generic standard cell library (i.e. tsmc 90nm) and one or two from my own library (characterized and custom made around the same 90nm pdk). If both library files are available in .db format, can we do it in a standard compiler like synopsys dc ? Or should I have to integrate my .db with the generic one (But I suppose this is not possible as the generic one is not open access) ?
Hi, thanks for the response. Now suppose that both .dbs have an inverter gate which matches the behavior RTL "~" operation. How can I blacklist a the inverter of the std_cell, and make the tool (i.e. design compiler) to pick the one in my .db ?
Anuradha
PS : both should be in target_library or link_library ?
Hi, thanks for the response. Now suppose that both .dbs have an inverter gate which matches the behavior RTL "~" operation. How can I blacklist a the inverter of the std_cell, and make the tool (i.e. design compiler) to pick the one in my .db ?
Anuradha
PS : both should be in target_library or link_library ?