Synthesisable Array initialization of static values in Verilog

phaneendra.raguru · Apr 29, 2014

Hi,
i need an array of static values such as

Code:

   reg [7:0] s_box [0:3][0:3] = '{'{8'h0,8'h1,8'h2,8'h3},
                                '{8'h10,8'h11,8'h12,8'h13},
                                '{8'h20,8'h21,8'h22,8'h23},
                                '{8'h30,8'h31,8'h32,8'h33}};

It is compiling in System Verilog but not in Verilog.
Please suggest me the suitable synthesisable verilog code where i can initialize static values

jbeniston · Apr 30, 2014

Verilog 1995 or 2001? They have different support for multidimensional arrays.

You can try to split out the initialisation.

wire [] x[];
assign x[0] = ....;
assign x[1] = ....;

Synthesisable Array initialization of static values in Verilog

phaneendra.raguru

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jbeniston

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Synthesisable Array initialization of static values in Verilog

phaneendra.raguru

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jbeniston

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