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In Verilog, you can use the black_box attribute to specify a module as a black box:


[CODE](* black_box *)

module my_macro (...);

endmodule

[/CODE]

In VHDL, you can use black_box synthesis directives:

[CODE]attribute black_box : string;

attribute black_box of my_macro : entity is "true";

[/CODE]


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