[Synthesis] Why need to define clock?

Hello All,

When we converting RTL to Gate Level Netlist, why we need to define clock during synthesis?

Regards,
Maulin

Hi,

While converting RTL to Gate level net-list, we will guide the tool for picking fast, less leaky cells using clock information.
That is the main reason for clocks/constraints.

Thank you very much.

Hi.

It is also necessary to define clock during synthesis because it's allows the synthesizer to perform STA-analysis, to recognize critical paths related to clocks and to optimize it.

Best regards,
Kuxx.

If we do not define clock, than what happened? Synthesis failed means shows the error/message or it just create the RTL to Gate Level netlist?

If we do not define clock synthesis tool will not calculate and optimize timing, just only logical synthesis of netlist will be performed. You will have a lot of timing problems such as setup, max transition and capacitance violations at desired clock frequency.

Best regards,
Kuxx.

maulin sheth said:

If we do not define clock, than what happened? Synthesis failed means shows the error/message or it just create the RTL to Gate Level netlist?

Click to expand...

-> RTL -> Gates conversion doesn't need clock definition.
-> you can use any other constraints to define the timing for your design(like max delays etc).
-> Clock constraints will easy your process between SP and EP. Else for every SP and EP, you need to write down the constraints.
-> If you don't define the timing constraints, tool will pick random cells and synthesize and provide you the netlist. when you take this netlist for P&R, signoff, you don't get correlation.
Which means, you need to use the same constraints (with variations) in Synthesis as well as signoff.

More over, you don't get any Error/Warning for not defining clock. what you get is unconstrained paths. If you know how to take care of unconstrainted paths, then its not necessary to define clocks.

Hi
what is SP and EP?

SP : Start Point
EP: End point .

For every timing paths, SP will be either clock pin or Input Port and EP is Register D pin or Output Port.

Thanks Sam

Thank you very much.

Synthesis usally comprises of the following : 1> Read library, 2> read hdl (analyze & elaborate) and then we do compile.
Clocks are usally defined in SDC or some constraint file. You will not need this constraint file unless you reach the compile phase.
After doing synthesis we analyze the reports for timing, area and congestion etc.. because if these cannot be met in the synthesis phase then later it would be more challenge. Now, in order to infer that we have to ensure that DC/RTL compiler has optimized the design.(compile) As we know that any optimization requires constraints hence we have to specify clocks and additional constraints like output_delay, input_delay, set_drive, set_load etc...
In case you do not want to add clocks and just want to optimize few paths, then you can use set_max_delay/set_min_delay and do it.
However, note that without the clock definitions you cannot even do report_timing and synthesis wihtout STA is handicapped.

Ro9ty