synthesis timing violation after MBIST insertion

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sumanth495

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hi friends,

presently i am doing synthesis with Mbist inserted RTL(mbist insertion has done by Tessent Mbist tool). after synthesis(even after incremental optimization) i am seeing a timing violation.
violating path is from memory "CLK pin" to some "GO_ID_REG*". this GO_ID_REG is inserted by tessent tool itself.
Timing slack : -261ps (TIMING VIOLATION)
Start-point : fifo4/ram_aes_fifo4/CLKA
End-point : fifo4/top_AES_ClkLabel4_MBIST1_MBIST_I1/MBIST_CTL_COMP/GO_ID_REG_reg_53/D

without Mbist insertion synthesis timing is clean.
please suggest me a solution to get timing violation clean(with out redusing the frequency)?

thanks
sumanth
 

Hi, MBIST must add some combination logic (usually MUX) at the input/output of the memory cells, this will of cause causing timing margin reduced after MBIST insertion. So you RTL need researved some timing margin for MBIST.
And for your case, it seems the violation points is in MBIST logic itself and I don't think it have some relationship with your function clcok. So, do you think you can mark these MBIST logic as false path, reference to your function clock.
 
hi yang,
thanks for your reply. actually this MBIST logic is operated in same functional clock.
my doubt is, can i put false path in the same clk domain?
here both start and end points are operated in same clk domain.
Start-point : fifo4/ram_aes_fifo4/CLKA
End-point : fifo4/top_AES_ClkLabel4_MBIST1_MBIST_I1/MBIST_CTL_COMP/GO_ID_REG_reg_53/D
 

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