akp494
Member level 1
Synthesis problem
I'm using index to access some bits of a shift register as this index changes values depending on some conditions.
in VHDL the piece of code looks like this:
a<= reg(ptr+1 downto ptr) where 'a' is a two bit vector.
When I try to synthesize the above piece of code,Synopsys DC says a constant is expected as the index.
In my opinion the synthesis tool should be upgraded to infer these kind of implementations. Here 'reg' is defined, "a" is defined and also "ptr" is defined and hence the tool shouldn't ideally see a problem in implementing this.
I'm using index to access some bits of a shift register as this index changes values depending on some conditions.
in VHDL the piece of code looks like this:
a<= reg(ptr+1 downto ptr) where 'a' is a two bit vector.
When I try to synthesize the above piece of code,Synopsys DC says a constant is expected as the index.
In my opinion the synthesis tool should be upgraded to infer these kind of implementations. Here 'reg' is defined, "a" is defined and also "ptr" is defined and hence the tool shouldn't ideally see a problem in implementing this.