Synthesis problem as constant is expected as the index!

[akp494]

Synthesis problem

I'm using index to access some bits of a shift register as this index changes values depending on some conditions.
in VHDL the piece of code looks like this:
a<= reg(ptr+1 downto ptr) where 'a' is a two bit vector.

When I try to synthesize the above piece of code,Synopsys DC says a constant is expected as the index.

In my opinion the synthesis tool should be upgraded to infer these kind of implementations. Here 'reg' is defined, "a" is defined and also "ptr" is defined and hence the tool shouldn't ideally see a problem in implementing this.

 

[hawk]

Re: Synthesis problem

what is the dc version you use???
what is the version of the simulator you use??

 

[akp494]

Re: Synthesis problem

Hello Hwak
I am using DC version 2003.12 . I guess it's pretty latest one.

 

[hawk]

Re: Synthesis problem

you should think as HW not SW,
tell exactly to dc what you mean.
e.g. if you add 1, you should add 1'b1 (like in verilog) etc'.

 

[akp494]

Re: Synthesis problem

Hello Hawk
I guess you go it wrong.

Let me explain the problem in a different way.

Suppose I have the following signal declarations.

signal reg : std_logic_vector(15 downto 0);
signal ptr : integer;
signal a : std_logic_vector(1 downto 0);

Then at some place in the code if I say

a<= reg(ptr+1 downto ptr)


Now if I try to synthesize this code using DC it is giving an error at the above statement showing the following comment.
"A Constant is expected as index"


Is there any work around for this?? Is it the problem with the tool.

 

[rol73]

Re: Synthesis problem

Sorry, my solution was already posted in another post... I've deleted it

-- Modified by the author