Anay
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Hi
I am writing verilog code for data compression techniques and I want to write 'z' in memory module. Also I would like to compare these 'z' values with logic 1 and logic 0. I know we can do it in simulation but what about synthesis. Can I do the same??? Is there any remedy to above problem.
Thank you,
Anay
I am writing verilog code for data compression techniques and I want to write 'z' in memory module. Also I would like to compare these 'z' values with logic 1 and logic 0. I know we can do it in simulation but what about synthesis. Can I do the same??? Is there any remedy to above problem.
Thank you,
Anay