synthesis of the rtl

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sun_ray

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What will following synthesize to?

always @ ( posedge clk or negedge rst)
begin
b <= a;
c <= b;
d = c;
end
 

its 2 flop design , first flop will be Flop_A , second flop will be FLOP_B , c will optimized and output of FLOP_B will be "d"

Rahul
 

its 2 flop design , first flop will be Flop_A , second flop will be FLOP_B , c will optimized and output of FLOP_B will be "d"

Rahul

What will be the input and output of FLOP_A? What will be the input of FLOP_B? Why will c be optimized?

Regards
 

What will be the input and output of FLOP_A? What will be the input of FLOP_B? Why will c be optimized?

Regards

input will be a for FLOP_A , output will be b for FLOP_A, input for FLOP_B will be b , and output of FLOP_B will be d.

C will optimized as at the end of simulation cycle , c and d will be having same value ..
 

C will optimized as at the end of simulation cycle , c and d will be having same value ..

Why will c and d have same value at the end of simulation?
What is the significance of achates in rahul.achates? Is your surname achates?
 

Why will c and d have same value at the end of simulation?
What is the significance of achates in rahul.achates? Is your surname achates?

haha .. Nice question. My surname is not achates ..its " Jain "

see below about the achates -- failthful friends
https://en.wikipedia.org/wiki/Achates

one more reason is , it is very rare and if you want to make user name any site , this name will be unique.

back to topic,

c and d will optimized because of blocking statement.

whatever value c having , D will also have same value , synthesis tool may put some buffer or just a wire connection ..

Rahul
 

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