synthesis of module with parameter "n" or `define "n"

[manchal]

my code is:
module e8_coltask(aa,bb,clk,result);
`define n 7
// parameter n=7; (n either as define or parameter)
input [`n:0] aa,bb;
input clk;
output [15:0] result;

It gets simulated,and gives correct result,but with synthesis it gives error :
INTERNAL_ERROR:Xst:cmain.c:3483:1.56.16.1 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at https://www.xilinx.com/support.
I couldn't get it.pls help.

 

[rca]

The define need to be define out side the module, no?

 

[jbeniston]

Contact Xilinx as it says. Whether you use a parameter or a define probably isn't the real problem, it's whatever code is in that module.