Synthesis of Integer in Verilog

ash72 said:

Hello,

I understand that it's not a good idea to use integers in RTL that is to be synthesized. In the following code, it will generate 32 bit incrementor. But my question is on the continuous assignment.

integer I;
always @(posedge Clock)
if ( Reset || (I == 255) )
I <= 0;
else I <= I + 1; //32-bit incrementor

wire [7:0] Count = I;

Will the wire assignment generate an eight bit counter? Or will it simply synthesize into an 8 bit bus.
Thanks.

Click to expand...

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
var logic [31:0] I; //The "var" isn't really needed because the SystemVerilog
                           //EDA tool you're using will normally take a "logic" type assigned
                           //to from a procedural block to be a variable -- I just wanted to make it
                           //clear that it's indeed a variable.
always_ff @(posedge Clock)
begin
        if (Reset) I <= '0;
        else if (I == ($pow(2, 32) - 1)) I <= 0;
        else I <= I + 1;
end
 
logic [31:0] Count = I;

jdb2 said:

There are several problems with your code. First, you're using the integer type, which isn't always synthesizable -- you should use a reg type or logic type ( as it appears you code is SystemVerilog from the implicit continuous assignment ) for the counter variable ( Also, the "integer" data type is a 2-state type which might not be desirable ). Second, you have your count limit detection code mixed in with your synchronous reset code which could cause problems with synthesis. Lastly, due to your code resetting the count when it reaches 255, you're actually modelling an 8-bit incrementor, not a 32-bit incrementor and besides that, you're assigning the integer's value to an 8-bit net which will truncate the value in the integer "I" variable. Here is the corrected SystemVerilog code :

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
var logic [31:0] I; //The "var" isn't really needed because the SystemVerilog
                           //EDA tool you're using will normally take a "logic" type assigned
                           //to from a procedural block to be a variable -- I just wanted to make it
                           //clear that it's indeed a variable.
always_ff @(posedge Clock)
begin
        if (Reset) I <= '0;
        else if (I == ($pow(2, 32) - 1)) I <= 0;
        else I <= I + 1;
end
 
logic [31:0] Count = I;

---

Hope this helps,

jdb2

Click to expand...

barry said:

Since when aren't integers synthesizable?

Click to expand...

FvM said:

By omitting "(I == 255)" you are changing the effective variable width from 8 to 32 bit. Why?

Click to expand...

jdb2 said:

( Also, the "integer" data type is a 2-state type which might not be desirable ).

Click to expand...